CSNL

Welcome to CSNL!

[Sep 2022] - Welcome Jihyun Kim and Xiangyu Wu to the lab! 

[Sep 2021] - Welcome Sanzhar, Yassawe, Gilbert and Tho to the lab! 

[Mar 2021] - Welcome Hyuntaek Cho (M.S) and Cheryl to the lab!

0
Papers
0
Students

NEWS ! 

OPENINGS : We are actively recruiting students that are interested in research computer architecture, GPU, hardware security, and deep learning architectures. If you are interested, please contact us at jjk12 at kaist dot edu.

  • Congratulations, Hans! Our "VVQ: Virtualizing Virtual Channel for Cost-Efficient Protocol Deadlock Avoidance" paper has been accepted on HPCA 2023.
  • Congratulations, Jiho! Our "Networked SSD: The Flash Memory Interconnection Network for High-Bandwidth SSD" paper has been accepted on MICRO 2022.
  • Congratulations, Hans! Our "Dynamic Global Adaptive Routing in High-radix Networks" paper has been accepted on ISCA 2022.
  • Congratulations! Our "Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD" paper has been accepted on IEEE CAL 2021.
  • Congratulations! Our "Ghost Routing to Enable Oblivious Computation on Memory-centric Networks" paper has been accepted on ISCA 2021. 

Our lab

our
Research
AREA

Computer
Architecture

Explore next-generation computer architecture, including deep learning accelerators, memory systems, on-chip networks, and scale-out systems.

Interconnection
Networks

High-performance and reliable interconnection network design on heterogeneous systems.
Network-on-chip architecture.

Hardware
Security

Micro-architectural attacks on parallel architecture (GPU) and server-scale NUMA system.

Recent
Publications

  • Oct 2022 – Congratulations, Hans! Our “VVQ: Virtualizing Virtual Channel for Cost-Efficient Protocol Deadlock Avoidance“ paper has been accepted on HPCA 2023.
  • July 2022 – Congratulations, Jiho! Our “Networked SSD: The Flash Memory Interconnection Network for High-Bandwidth SSD” paper has been accepted on IEEE MICRO 2022. 
  • Mar 2022 – Congratulations, Hans! Our “Dynamic global adaptive routing in high-radix networks“ paper has been accepted on IEEE ISCA 2022.
  • Oct 2021 – Congratulations! Our “Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD” paper has been accepted on IEEE CAL 2021.
  • Jun 2021 – Congratulations! Our “Ghost Routing to Enable Oblivious Computation on Memory-centric Networks” paper has been published on ISCA 2021. 
  • Aug 2021 – Congratulations! Our GPU security (GPU covert channel) paper has been accepted on MICRO 2021.
  • Feb 2021 – Congratulations! Our “The Case for Dynamic Bias in Global Adaptive Routing” paper has been accepted on IEEE CAL 2021.
  • Dec 2020 – Congratulations! Our GPU security (Trident – side channel attack) and Deadlock (BoomGate – deadlock avoidance) papers have been accepted on HPCA 2021. 
  • Sep 2020 – We are currently recruiting new MS students in the area of hardware security and deep learning architecture.  If you are interested, please contact the professor.
  • Sep 2020 – Welcome to Jeremy (Ph.D.) and Sheryl (Ph.D) to the lab!
  • Aug 2020 – One paper (on TLB in GPUs) and one poster (on NoC in GPUs) will appear in PACT’20.
  • Mar 2020 – Collaboration work with Facebook on Deep Learning Training has been published on ArXiv
    https://arxiv.org/abs/2003.09518
  • Mar 2020 – Welcome Jangpyo (M.S.) and Jihyun (M.S.) to the lab!
  • Feb 2020 – Collaborative work (NeuMMU – ASPLOS’20) and (Griffin – HPCA’20) have been accepted!
  • Nov 2019 – Ghost Routers: Energy-efficient Asymmetric Multicore Processors with Symmetric NOCs. [NOCS’19]
  • Jun 2019 – A Novel Covert Channel Attack Using Memory Encryption Engine Cache. [DAC’19]
  • Oct 2018 – Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture. [MICRO’18]
  • Jun 2018 – TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks. [ISCA’18]
  • Apr 2018 – BebeCODE: Collaborative Child Development Tracking System. [CHI’18]
  • May 2017 – PlayBetter: A Phone-based Baby Play Support System for Childcare Bystander Parents. [CHI’17]
  • Apr 2017 – History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers. [ASPLOS’17]