our Research AREA


Computer

Architecture

Explore next-generation computer architecture, including deep learning accelerators, memory systems, on-chip networks, and scale-out systems.


Interconnection

networks

High-performance and reliable interconnection network design on heterogeneous systems.
Network-on-chip architecture.


Hardware

security

Micro-architectural attacks on parallel architecture (GPU) and server-scale NUMA system.

UPDATE (News)

  • Dec 2020 – Congratulations ! Our GPU security (Trident – side channel attack) and Deadlock (BoomGate – deadlock avoidance) papers have been accepted on HPCA 2021. 
  • Sep 2020 – We are currently recruiting new MS students in the area of hardware security and deep learning architecture.  If you are interested, please contact the professor.
  • Sep 2020 – Welcome to Jeremy (Ph.D.) and Sheryl (Ph.D) to the lab!
  • Aug 2020 – One paper (on TLB in GPUs) and one poster (on NoC in GPUs) will appear in PACT’20. 
  • Mar 2020 – Collaboration work with Facebook on Deep Learning Training has been published on ArXiv
    https://arxiv.org/abs/2003.09518
  • Mar 2020 – Welcome Jangpyo (M.S.) and Jihyun (M.S.) to the lab! 
  • Feb 2020 – Collaborative work (NeuMMU – ASPLOS’20) and (Griffin – HPCA’20) have been accepted! 
  • Nov 2019 – Ghost Routers: Energy-efficient Asymmetric Multicore Processors with Symmetric NOCs. [NOCS’19]
  • Jun 2019 – A Novel Covert Channel Attack Using Memory Encryption Engine Cache. [DAC’19]
  • Oct 2018 – Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture. [MICRO’18]
  • Jun 2018 – TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks. [ISCA’18]
  • Apr 2018 – BebeCODE: Collaborative Child Development Tracking System. [CHI’18]
  • May 2017 – PlayBetter: A Phone-based Baby Play Support System for Childcare Bystander Parents. [CHI’17]
  • Apr 2017 – History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers. [ASPLOS’17]